如果输入信号为in,输出信号为out,则以下程序的功能是?() reg int_reg; always@( posedge clk or negedge rst) begin if (!rst) int_reg <= 0; else int_reg <= in; end assign out = ~ int_reg & in;
【判断题】第三学段学生习作时应能根据表达需要,正确使用常用的标点符号。
已知时钟信号clkin的频率为100mhz的方波信号,下面程序中clkout信号的占空比为( )。 module function(rst,clkin, clkout); input clkin, rst; output wire clkout; reg[2:0] m, n; reg clk1, clk2; assign clkout=clk1|clk2; always @(posedge clkin) begin if(!rst) begin clk1<=0; m<=0; end else begin if(m==4) m<=0; else m<=m 1; if(m<2) clk1<=1; else clk1<=0; end end always @(negedge clkin) begin if(!rst) begin clk2<=0; n=0; end else begin if(n==4) n<=0; else n<=n 1; if(n<2) clk2<=1; else clk2<=0; end end endmodule
以下程序描述的状态机是什么类型的?() always@(current_state or itrig or dy_cnt) begin case( current_state ) s0: begin dy1 = 0; if (itrig) begin next_state = s1; end else next_state = s0; end s1: begin if (dy_cnt <= dy_time) begin next_state = s1; dy1 = 1; end else begin next_state = s2; dy1 = 0; end end s2: begin dy1 = 0; next_state = s0; end default: begin next_state = s0; end endcase end